1/8 october 1999 AN1157 application note connecting the 80960ja microcontroller to m29 series flash memories contents n introduction n advantages of flash n flash bus architecture n 80960ja bus architecture n timing requirements n conclusion introduction this application note describes a method to connect an m29w004b flash memory to an 80960ja microcontroller. the application note can be used as a reference for other flash memory devices from stmicroelectronics. the m29w004b is a 4 mbit (512kb x 8) flash memory from st- microelectronics, with asymmetrical block sizes. other flash parts that can be used in place of the m29w004b include the m29w002b, m29w008a and m29w116b. the tsop40 pack- ages of these memories are pin-compatible with the m29w004b, allowing them to be used in place of an m29w004b. designers should track their pcbs for the extra address lines of the larger parts so they can be accommodat- ed, if necessary, in the future. the 80960ja is a member of intels i960 family of embedded risc microprocessors. the i960 family has a large range of uses from i/o processors to computer peripherals such as printers. advantages of flash flash memories can be used to store both code and data for the i960 microprocessor. unlike eproms the data in flash memories can be changed by the microprocessor. this en- ables non-volatile user data to be stored in the flash. field up- grades of the application code can be performed without any disassembly, unlike eprom solutions. it is usual to write separate boot and application programs so that the application program can be upgraded without changing the boot program. if the upgrade fails then the processor will still boot and it will be possible to reattempt to upgrade the ap- plication. the boot code should be programmed into the flash before the flash is fitted to the circuit board, otherwise it may not be possible to boot the microprocessor. often the block containing the boot program is protected so it cannot become corrupt.
AN1157 - application note 2/8 flash bus architecture take a look at the bus on the m29w004b, figure 1 shows the logic diagram. figure 1. m29w004b logic diagram the memory has separate address and data buses, the multiplexed bus of the 80960ja will need to be decoded and latched in order to connect correctly. the control lines are chip enable (e ), output enable (g ) and write enable (w ), these too will require additional logic. the reset/block temporary unprotect pin (rp ) accepts three states: reset (v il ), not reset (v ih ) and block temporary unprotect (v id ). reset and not reset are the usual signals for a system reset line. the third state, block temporary unprotect is used to temporarily unprotect blocks that have been specifically protected in the memory. many applications do not protect any blocks and therefore connect the rp pin directly to the system reset signal. figure 2 gives an example of how the connection between the system r eset line and the m29w004bs rp pin can be made. the circuit makes use of a jumper to enable block temporary unprotect. many ap- plications will provide the 12v from an external source, in which case the jumper can be replaced by a connector. the advantage with the circuit, as it stands, is that the system reset will override block tem- porary unprotect and cause the flash to reset. only four additional components are required. before the jumper is inserted, and when reset is high, v ih , rp is connected to 3v through the 10k w resistor and the diode. the current required by rp is very low, in the order of 1 m a at 3v. the voltage drop in the resistor and the diode at these currents will keep rp very close to 3v. when the jumper is fitted the diode ceases to conduct and rp rises to 12v as the capacitor charges. the time-constant of a 10k w re- sistor and a 50pf capacitor is 500ns, satisfying the t phphh rise-time requirements of the m29w004b. dur- ing a reset, reset is low, v il , and the jfet is switched on, bringing rp close to ground. the current consumption during a reset rises due to the current through the 10k w resistor. although the use of a jumper may not be the most elegant solution, it is a practical one because it main- tains the security level offered by block protection. there is little point in having the block temporary un- protect pin under software control. the whole point of the block protection feature is to protect against software failure. allowing the block temporary unprotect feature to be under the control of software is nearly equivalent to not protecting the blocks in the first place. ai02954 19 a0-a18 w dq0-dq7 v cc m29w004bt m29w004bb e v ss 8 g rp rb
3/8 AN1157 - application note figure 2. reset/block temporary unprotect circuit 80960ja bus architecture the 80960ja's bus architecture is very different from the architecture of the m29w004b. it is a synchro- nous interface, with a multiplexed bus and burst mode capability. there are many different control lines, none of which interface directly with the flash. the bus supports 8-bit, 16-bit and 32-bit transfers, it sup- ports software-transparent reading and writing of unaligned data. three of the five basic bus states are of interest to a design interfacing an m29w004b to the 80960ja, the t a state (address), t w/d (wait/data) and t r (recovery). during the t a state the address is output on the multiplexed bus, during the t w/d state the data is read or written to the bus and during the t r state the memory has time to release the bus. the address needs to be latched during the t a state; the flash memory requires the address to be valid during the entire read or write cycle. the 80960ja includes an output, ale (address latch enable), which can be used to latch the address at the correct time. the address requires decoding to a chip select sig- nal, which is low when the microprocessor addresses the flash. during the t w/d state the r/w signal re- quires decoding to output enable and write enable signals; a wait-state generator is required to signal the microprocessor that the flash is ready. finally, during the t r state the flashs chip enable must be brought high for the flash to release the bus. the accesses required can be encoded into a state machine (best when one or more wait-states are required). for zero wait-states a simpler circuit can be devised, figure 3 shows a simple connection. the chip select logic works directly off the multiplexed address/data bus. by oring the cs with ads the input of the d-type only clocks a valid chip select when a valid flash address is on ad19-ad31. the chip select is latched to provide the flash with the chip enable, e , signal. the output enable signal for the flash is taken directly from the w/r signal, and inverted to give the write enable signal. the rdyrcv signal that tells the microprocessor that the flash is ready is generated directly from the chip enable sig- nal, since the 80960ja is a synchronous bus this signal is only sampled when the clock rises, and there- fore chip enable generates the correct waveform. ai02939 10k w 50pf 3v 12v reset rp
AN1157 - application note 4/8 figure 3. connection between the 80960ja and the m29w004b ai02940 a2-a18 w dq0-dq7 m29w004bt e g rp rb ad0-ad31 80960ja reset/block temporary unprotection circuit latches a0 a1 be0 be1 ad2-ad18 ale ad19-ad31 reset clkin clkin ads w/r control logic chip select logic d q ads w/r clkin e w g ad19-ad31 rdyrcv rdyrcv simple, zero wait-state control logic cs
5/8 AN1157 - application note in order to boot the 80960ja from the code in the m29w004b it is necessary to map the m29w004b to the address space where the 80960ja holds its initialization boot record (feff ff30h-feff ff5f). the 80960ja reads the initialization boot record using 8-bit accesses, making an 8-bit flash part very suitable for booting the 80960ja. since the 80960ja looks at the top of its external memory space for the initialization boot record the usual choice of flash is a top-boot block part, such as the m29w004bt. the m29w004bt can be mapped to have its boot block at the address of the initialization boot record, all the initialization data structures and the boot code can be put in the boot-block of the m29w004bt. typically the application software would not be run directly from an 8-bit flash. 8-bit flash is still an excel- lent storage media for application software since it has a fast access time per byte, it is simple to use and is relatively inexpensive compared to 16-bit and 32-bit flash. the boot code should copy the application code to a 32-bit wide memory (such as dram) and run it from there. there are flash memories that are suitable for running the application code directly from the flash; they include burst/page mode bus inter- faces to minimize the access times and dual-bank architectures so the program can be run from flash while the flash is erasing or programming. a 16-bit or 32-bit wide flash should be used with the 80960ja processor if the program is to be run directly from it.
AN1157 - application note 6/8 timing requirements each of the bus states for the 80960ja lasts one clock period, for a 16.67mhz clock the access time will be 60ns less the delay in the d-type flip-flop. the following timings have been derived for a flip-flop with a 5ns delay. table 1 and figure 4 shown the read timings; table 2 and figure 5 show the write timings. table 1. principal read timing requirements figure 4. principal read timing waveform m29w004b 80960ja symbol 55 70 90 5ns flip-flop t avav 55 70 90 60 t av qv 55 70 90 60 t elqv 55 70 90 55 t glqv 30 30 35 96.5 t ehqz 20 25 30 55 t oh 000 0 ai02999 tavqv telqv toh a0-a17 e ad0-ad31 dq0-dq15 g tglqv tehqz address valid data out t a t d t r t a tavav cklin
7/8 AN1157 - application note table 2. principal write timing requirements, write enable controlled figure 5. principal write timing waveforms from the timings it can be seen that a 55ns flash is required to provide zero wait-state access with a 5ns flip-flop. for slower parts it will be necessary to implement a state-machine to add additional wait-states. conclusion the m29w004a and other stmicroelectronics flash can be connected to the 80960ja as the boot rom with zero wait-state access. the m29w004b provides embedded systems with non-volatile data storage and the ability to perform field upgrades of application software without disassembly. m29w004b 80960ja symbol 55 70 90 5ns flip-flop t avav 55 70 90 60 t eleh 40 45 45 60 t dveh 25 30 45 48.5 t ehel 30 30 30 120 t elax 40 45 45 115 ai02998 telax tdveh a0-a17 e ad0-ad31 dq0-dq15 w teleh address valid data in t a t d t r t a tavav cklin
AN1157 - application note 8/8 if you have any questions or suggestion concerning the matters raised in this document please send them to the following electronic mail address: ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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